Extreme scale general-purpose processor

Research in progress.

Target:
5nm
>60 TFLOPS
Direct graphics rendering (no API)

Core pipeline:
[IF] [BT] [BO] [ID] [EX] [MEM] [WB]

BT = Binary Translator
BO = Binary Optimizer

Dies configuration:
[CCCC][MMMM][CCCC]
[CCCC][MMMM][CCCC]
[CCCC][MMMM][CCCC]
[CCCC][MMMM][CCCC]

Memory:
NVRAM--CHIP--NVRAM
Software pre-scheduling (optional)
add $r13 = $r3, $r0
sub $r16 = $r6, 3
;;
shl $r13 = $r13, 3
shr $r15 = $r15, 9
ld.w $r14 = 0 [$r4]
;;


;; = NOP